1. Technical Field
The present invention relates to the field of radio communication, and more particularly, to multi-channel radios.
2. Discussion of Related Art
FIGS. 1A and 1B are high level schematic block diagrams prior art receivers 91 and transmitters 92, respectively. Receiver 91 (FIG. 1A) is a super-heterodyne receiver which converts an incoming signal that may have different carrier frequencies into a signal at a predefined intermediate frequency, from which the information modulated into the incoming signal is decoded. Receiver 91's bandwidth is illustrated schematically in diagram 60 referring to the VHF and UHF radio regions (very high frequencies, 30-300 MHz, and ultra-high frequencies, 300-3000 MHz, respectively) of the electromagnetic spectrum. The signal is received through antenna 91A, its bandwidth is narrowed (schematically illustrated in diagram 61) by a Band Pass Filter (BPF) and Digital Control Attenuator (DCA) components and the signal amplified by a low-noise amplifier (LNA) at stage 91C. Then, at stage 91D, a frequency mixer is used to modify the carrier frequency into a first intermediate frequency (IF1) by mixing the signal with a frequency generated by a respective synthesizer to yield signal 62 at the intermediate frequency. The signal from stage 91D is typically transformed again by a stage 91E into another intermediate frequency (IF2) to remove disturbing frequencies such as mirror frequencies and adjacent frequencies from blocking signals, and yield signal 63 that may then be converted into digital information by Analog to Digital Converter (ADC) 91F. Stages 91C-91F represent the de-modulation stage 91B of a single received channel, the digital information from which is then delivered for further processing (stage 91G) by field-programmable gate array (FPGA) and digital signal processing (DSP) or microprocessor (μP).
Prior art multi-channel receivers 91 employ multiple de-modulation stages 91B, each tuned to receive a different frequency by generating correspondingly different frequencies by the synthesizers (intermediate frequencies IF1, IF2 are typically the same for all channels), to yield multiple channels.
Transmitter 92 (FIG. 1B) has a structure that basically corresponds to the structure of receiver 91. Processing elements 92A (e.g., DSP, μP, FPGA) generate digital signals which are fed into one or more modulation stage(s) 92B and are converted by corresponding digital to analog converter(s) 92C. The analog signal is then mixed at stages 92D, 92E with synthesized frequencies to reach the carrier frequency range and then filtered and amplified in stage 92F (by low pass filter—LPF, driver and power amplifier and harmonic filter) to yield a signal 70 which is broadcasted by antenna 92G. It is noted that equivalent components in receiver 91 and transmitter 92 were denoted by different numerals in order to streamline their explanation. Clearly, processing stages 91G, 92A and antennas 91A, 92G may be implemented as single components, respectively, in a transceiver that combines receiver 91 and transmitter 92.
The following patents and patent applications are incorporated herein by reference in their entirety: U.S. Patent Publication No. 20130178179 teaches a subsampling receiver using interstage off-chip RF band pass filter; U.S. Patent Publication No. 2014062614 teaches a switching circuit for selecting a frequency band; Chinese Patent Document No. 101452013 teaches a switch filter array case system for calibration of a spectrum analyzer and a vector signal analyzer; and U.S. Pat. No. 3,855,556 teaches a selectable frequency bandpass filter that modulates an analog signal by applying variable delays on the input signal.